The present invention relates to a semiconductor device and a manufacturing method therefor, and more particularly to a semiconductor device capable of being diced and die-bonded stably and a manufacturing method to make such devices.
Recently, as electronic appliances have become more compact, semiconductor chips used therein have also been required to become more compact and the scale of integration required has become larger. In this trend, the spacing between semiconductor elements in a semiconductor chip, and the width of scribing line defined between adjacent semiconductor chips are being narrowed. Furthermore, peripheral circuits and aluminum wirings on the semiconductor chip are often formed at a position extremely close to the marginal edge of the semiconductor chip.
FIG. 5 and FIG. 6 show a conventional semiconductor device dicing method.
As shown in FIG. 5 and FIG. 6, on the surface of a semiconductor wafer 1, an oxide film for semiconductor element isolation (so-called LOCOS oxide film) 2 is selectively formed. In the region separated by the oxide film 2 on the surface of semiconductor wafer 1, transistors, capacitors and other semiconductor elements are formed. Individual semiconductor elements are not shown in the drawings, and these semiconductor elements and the wiring for connecting them are collectively expressed as a semiconductor element region 3. On the surface of semiconductor element region 3, a protective film 4 composed of oxide film, nitride film or the like is formed. Between adjacent semiconductor element regions 3, 3, scribing line 5 is defined in order to divide the semiconductor wafer 1 into plural square-shaped semiconductor chips.
Accordingly, by rotating a dicing saw 6 composed of a disk-shaped blade having a diamond attached to the tip, at high speed, when the semiconductor wafer 1 is cut along the center line of the scribing lines 5 while moving in the direction orthogonal to the sheet of paper, the semiconductor wafer 1 can be divided into plural semiconductor chips 7, 8.
However, when the semiconductor wafer 1 is cut in this manner, since the hardness of the scribing line 5 is high, the dicing saw 6 applies an immoderate force to the semiconductor wafer I, and as a result cracks are formed in the peripheral portion of scribing line 5 as shown in FIG. 6. When the cracks propagate up to the oxide film 2, semiconductor element region 3 or protective film 4 as indicated by circle A in FIG. 6, the water (not shown) supplied to the semiconductor wafer 1 in order to cool off the heat generated due to high speed rotation and movement of the dicing saw 6 invades in to the crack area. Consequently, the reliability of the manufactured semiconductor chip is lowered. Such problem is more serious when the width of the scribing lines 5 is narrowed for the purpose of making finer structure and larger scale integration of semiconductor chips for miniaturizing electronic appliances.
Incidentally, conforming semiconductor chips separated from the semiconductor wafer 1 in the above dicing process may be adhered to a lead frame in a subsequent die-bonding process.
FIG. 7 and FIG. 8 relate to a conventional die-bonding method. In FIG. 7, the lower surface of a collet 9 is formed in a pyramidal shape, and a pipe 10 is affixed in the middle of the collet 9. On the surface of the semiconductor chip 8, an integrated circuit part 11 comprising oxide film 2, semiconductor element region 3 and protective film 4, as shown in FIG. 5 and FIG. 6, is formed. A part of scribing lines 5 is left over around the integrated circuit part 11.
Die-bonding is performed in the following manner. In the first place, the collet 9 is moved onto the conforming semiconductor chip 8 separated by the dicing process, and the air in the lower surface of the collet 9 is extracted in the direction of arrow B by vacuum means comprising a pipe 10 and a vacuum pump (not shown) attached to the upper end of the pipe 10. As a result, the semiconductor chip 8 is attracted to the lower surface of the collet 9, with the vicinity of the peripheral ridge of the semiconductor substrate in contact with the slope of the collet 9. Therefore, the integrated circuit part 11 does not contact with the collet 9. In this state, the collet 9 is moved onto the lead frame 12, and the semiconductor chip 8 is mounted on the lead frame 12. The surface of the lead frame 12 is preliminarily coated with an adhesive (not shown) such as silver paste. Then, as shown in FIG. 8, by shaking (or vibrating) the collet 9 in the directions of arrows C, D in FIG. 8 while pressing the semiconductor chip 8 onto the lead frame 12 by the collet 9, that is, by, so to speak, scrubbing, the semiconductor chip 8 is adhered to the lead frame 12.
At this time, since a force is directly applied to the peripheral edge of the semiconductor chip 8 by the slope of the collet 9, a crack may be formed from the vicinity of the edge of the semiconductor chip 8 to the inside of the semiconductor substrate as indicated by circle E in FIG. 8. In particular, when integrated circuit part 11 is formed with its periphery close to the outermost periphery of the semiconductor chip 8 (that is, when the scribing line 5 is narrow), or when the aluminum wirings in the integrated circuit part 11 are formed closely to the outermost periphery of the integrated circuit part 11, the cracks formed in the semiconductor substrate may reach up to the inside of the integrated circuit part 11. If the edge of the semiconductor chip 8 is broken, meanwhile, as shown in FIG. 9, the edge of the integrated circuit part 11 is pressed against the slope of the collet 9, and hence the integrated circuit part 11 may be directly destroyed.
Moreover, if cracks are formed in the scribing lines 5 or in the integrated circuit part 11, water may invade through the interface of the integrated circuit part 11 and semiconductor substrate, and therefore the reliability of the semiconductor device is lowered.
In the manufacturing methods of conventional semiconductor devices, as described herein, cracks are likely to be formed in the semiconductor substrate or other parts, whether in the scribing process or in the die-bonding process, and accordingly, production yield is lowered, or the reliability of the semiconductor device is lowered due to reduced humidity resistance.
It is hence a primary object of the invention to present a semiconductor device and a manufacturing method therefor capable of solving such conventional problems.
It is a first object of the invention to present a semiconductor device which is less likely to cause cracks in the semiconductor substrate in the scribing process or die-bonding process.
It is a second object of the invention to present a semiconductor device manufacturing method comprising a dicing step which is less likely to cause cracks in the semiconductor substrate.
It is a third object of the invention to present a semiconductor device manufacturing method comprising a die-bonding process which is less likely to cause cracks in the semiconductor substrate.
Meanwhile, the present applicant filed the Japanese patent application No. Sho. 63-23068 (Laid-open Patent No. Hei. 01-196850) to the Japanese Patent Office on Feb. 2, 1988, and the present application is a further improved version of the foregoing invention.